1. Field of the Invention
The present invention relates to a driving circuit which is adapted for use as a driver for driving S/T points in ISDN user-network interfaces or the like, and which has two output terminals for connection with a load, for supplying the load with a constant voltage changing in polarity at predetermined timing, through the output terminals.
2. Prior Art
Conventionally, as a line driver such as an S/T point driver for use in ISDN user-network interfaces, a driving circuit as shown in FIG. 1 is known. A bridge circuit 1 is formed of four n-channel MOS transistors (hereinafter referred to as "NMOS transistors") N1-N4 and driven by a constant current source 11. The bridge circuit 1 has two bridge output nodes A and B connected, respectively, to two output terminals (line output terminals) OUT1 and OUT2 for connection with a load Z. The NMOS transistors N1-N4 are selectively turned on by outputs from a selector circuit 4 such that the transistors N1, N4 are simultaneously turned on at a certain timing, while the transistors N2, N3 are simultaneously turned on at another timing, whereby a signal voltage changing in polarity is supplied to the load Z. The constant voltage source 11 is adapted to supply current in an amount exceeding an amount required for driving the load Z.
An NMOS transistor N7 is provided as a bypass circuit 3 for bypassing an extra amount of current from the constant current source 11 in response to output voltage supplied from the output terminals OUT1, OUT2 to the load z in order to always maintain the output voltage equal to constant reference voltage VREF. A differential amplifier circuit 2 feedback-controls the conductivity of the NMOS transistor 7. The differential amplifier circuit 2 is comprised of a current mirror circuit formed by NMOS transistors N5 and N6, to serve as an active load, and a pair of p-channel MOS transistors (hereinafter referred to as "PMOS transistors") P1 and P2 for differential amplification. One of the differential amplification PMOS transistors P1, P2 has an input terminal thereof supplied with the reference voltage VREF, and the other has an input terminal thereof supplied with a higher one of two output voltages from the two output nodes A, B of the bridge circuit 1, that is to be controlled. NMOS transistors N8 and N9 are provided as transfer gates for selecting either of the output voltages from the output nodes A, B and applying the same to the differential amplifier circuit 2.
Let it now be assumed that the NMOS transistors N2, N3 of the bridge circuit 1 are turned on, while the NMOS transistors N1, N4 are turned off. In this state, the output terminal OUT2 is grounded, and an output voltage appears at the output terminal OUT1. At this time, the NMOS transistor N8 as the transfer gate is turned on so that the output voltage at the output terminal OUT1 is fed back to the differential amplifier circuit 2, whereby the NMOS transistor N7 bypasses the extra amount of current from the constant current source 11 by which the current amount from the constant current source 11 exceeds the amount required for driving the load Z until the output voltage becomes equal to the reference voltage VREF. On the other hand, when the NMOS transistors N1, N4 are turned on, the output voltage produced at the output terminal OUT2 is fed back via the NMOS transistor N9 which is then turned on to the differential amplifier circuit 2 to effect output voltage control similarly to the above.
In recent years, there has been a growing demand for incorporating a line driver of this kind constructed as above into LSI's which can be driven by both a 5 volt power source and a 3 volt power source, with a demand for lowering the power supply voltage for LSI's in general. The construction of the line driver in FIG. 1, however, suffers from the problem that the NMOS transistors N8, N9 as transfer gates cannot perform the voltage transfer function as desired if the power supply voltage is lowered.
This problem will now be explained more in detail. The NMOS transistors N8, N9 are used as transfer gates whose sources and drains assume intermediate potentials. In the illustrated example, the terminals of the NMOS transistors N8, N9 on the PMOS transistor P2 side are considered to be the sources. Provided that the power supply voltage is designated by VDD and the threshold voltage of the NMOS transistors N8, N9 by VTH, when the gates of the NMOS transistors N8, N9 are driven by the power supply voltage VDD, the source potential can rise up to VDD VTH. For example, when VDD=5 volts, VTH=2 volts, and VREF=2 volts, the source potential can rise up to 3 volts, and therefore the output voltage from the output terminals OUT1, OUT2 can be surely maintained at the reference voltage VREF. However, when VDD=3 volts, even if the output terminal OUT1 or OUT2 assumes 2 volts or more, the NMOS transistors N8 or N9 will be turned off when the source potential rises to VDD-VTH=1 volt. In other words, the NMOS transistors N8, N9 cannot transfer voltage required for feedback control of the output voltage to the differential amplifier circuit 2.